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1. general description the 74aup2g04 is a high-performance, low-power, low-voltage, si-gate cmos device, superior to most advanced cmos compatible ttl families. schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire v cc range from 0.8 v to 3.6 v. this device ensures a very low static and dynamic power consumption across the entire v cc range from 0.8 v to 3.6 v. this device is fully speci?ed for partial power-down applications using i off . the i off circuitry disables the output, preventing the damaging back?ow current through the device when it is powered down. the 74aup2g04 provides two inverting buffers. 2. features n wide supply voltage range from 0.8 v to 3.6 v n high noise immunity n complies with jedec standards: u jesd8-12 (0.8 v to 1.3 v) u jesd8-11 (0.9 v to 1.65 v) u jesd8-7 (1.2 v to 1.95 v) u jesd8-5 (1.8 v to 2.7 v) u jesd8-b (2.7 v to 3.6 v) n esd protection: u hbm jesd22-a114-c class 3a. exceeds 5000 v u mm jesd22-a115-a exceeds 200 v u cdm jesd22-c101-c exceeds 1000 v n low static power consumption; i cc = 0.9 m a (maximum) n latch-up performance exceeds 100 ma per jesd 78 class ii n inputs accept voltages up to 3.6 v n low noise overshoot and undershoot < 10 % of v cc n i off circuitry provides partial power-down mode operation n multiple package options n speci?ed from - 40 cto+85 c and - 40 c to +125 c 74aup2g04 low-power dual inverter rev. 01. 16 january 2006 preliminary data sheet
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 2 of 18 philips semiconductors 74aup2g04 low-power dual inverter 3. quick reference data [1] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; s (c l v cc 2 f o ) = sum of the outputs. [2] the condition is v i = gnd to v cc . 4. ordering information table 1: quick reference data gnd = 0 v; t amb =25 c; t r =t f 3ns. symbol parameter conditions min typ max unit t phl , t plh high-to-low and low-to-high propagation delay na to ny c l = 5 pf; r l =1m w ; v cc = 0.8 v - 16.0 - ns c l = 5 pf; r l =1m w ; v cc = 1.1 v to 1.3 v 2.4 5.0 10.3 ns c l = 5 pf; r l =1m w ; v cc = 1.4 v to 1.6 v 1.8 3.6 6.4 ns c l = 5 pf; r l =1m w ; v cc = 1.65 v to 1.95 v 1.5 2.9 5.0 ns c l = 5 pf; r l =1m w ; v cc = 2.3 v to 2.7 v 1.2 2.4 3.9 ns c l = 5 pf; r l =1m w ; v cc = 3.0 v to 3.6 v 1.1 2.1 3.2 ns c i input capacitance - 1.0 - pf c pd power dissipation capacitance v cc = 1.8 v; f i = 1 mhz [1] [2] - 3.2 - pf v cc = 3.3 v; f i = 1 mhz [1] [2] - 4.3 - pf table 2: ordering information type number package temperature range name description version 74aup2g04gw - 40 c to +125 c sc-88 plastic surface mounted package; 6 leads sot363 74AUP2G04GM - 40 c to +125 c xson6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1.45 0.5 mm sot886 74aup2g04gf - 40 c to +125 c xson6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1 0.5 mm sot891
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 3 of 18 philips semiconductors 74aup2g04 low-power dual inverter 5. marking 6. functional diagram 7. pinning information 7.1 pinning table 3: marking type number marking code 74aup2g04gw p4 74AUP2G04GM p4 74aup2g04gf p4 fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram (one gate) mnb079 1a 1y 1 6 2a 2y 3 4 1 1 6 mnb080 3 1 4 mna110 a y fig 4. pin con?guration sot363 (sc-88) fig 5. pin con?guration sot886 (xson6) 74aup2g04 1a 1y gnd 2a 2y 001aad694 1 2 3 6 v cc 5 4 74aup2g04 gnd 001aad695 1a 2a v cc 1y 2y transparent top view 2 3 1 5 4 6
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 4 of 18 philips semiconductors 74aup2g04 low-power dual inverter 7.2 pin description 8. functional description 8.1 function table [1] h = high voltage level; l = low voltage level. fig 6. pin con?guration sot891 (xson6) 74aup2g04 gnd 001aad666 1a 2a v cc 1y 2y transparent top view 2 3 1 5 4 6 table 4: pin description symbol pin description 1a 1 data input 1a gnd 2 ground (0 v) 2a 3 data input 2a 2y 4 data output 2y v cc 5 supply voltage 1y 6 data output 1y table 5: function table [1] input output na ny lh hl
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 5 of 18 philips semiconductors 74aup2g04 low-power dual inverter 9. limiting values [1] the minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] for sc-88 packages: above 87.5 c the value of p tot derates linearly with 4.0 mw/k. for xson6 packages: above 45 c the value of p tot derates linearly with 2.4 mw/k. 10. recommended operating conditions table 6: limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +4.6 v i ik input clamping current v i <0v - - 50 ma v i input voltage [1] - 0.5 +4.6 v i ok output clamping current v o <0v - - 50 ma v o output voltage active mode and power-down mode [1] - 0.5 +4.6 v i o output current v o =0 vtov cc - 20 ma i cc quiescent supply current - +50 ma i gnd ground current - - 50 ma t stg storage temperature - 65 +150 c p tot total power dissipation t amb = - 40 c to +125 c [2] - 250 mw table 7: recommended operating conditions symbol parameter conditions min max unit v cc supply voltage 0.8 3.6 v v i input voltage 0 3.6 v v o output voltage active mode 0 v cc v power-down mode; v cc = 0 v 0 3.6 v t amb ambient temperature - 40 +125 c d t/ d v input transition rise and fall rate v cc = 0.8 v to 3.6 v 0 200 ns/v
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 6 of 18 philips semiconductors 74aup2g04 low-power dual inverter 11. static characteristics table 8: static characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = 25 c v ih high-state input voltage v cc = 0.8 v 0.70 v cc -- v v cc = 0.9 v to 1.95 v 0.65 v cc -- v v cc = 2.3 v to 2.7 v 1.6 - - v v cc = 3.0 v to 3.6 v 2.0 - - v v il low-state input voltage v cc = 0.8 v - - 0.30 v cc v v cc = 0.9 v to 1.95 v - - 0.35 v cc v v cc = 2.3 v to 2.7 v - - 0.7 v v cc = 3.0 v to 3.6 v - - 0.9 v v oh high-state output voltage v i = v ih or v il i o = - 20 m a; v cc = 0.8 v to 3.6 v v cc - 0.1 - - v i o = - 1.1 ma; v cc = 1.1 v 0.75 v cc -- v i o = - 1.7 ma; v cc = 1.4 v 1.11 - - v i o = - 1.9 ma; v cc = 1.65 v 1.32 - - v i o = - 2.3 ma; v cc = 2.3 v 2.05 - - v i o = - 3.1 ma; v cc = 2.3 v 1.9 - - v i o = - 2.7 ma; v cc = 3.0 v 2.72 - - v i o = - 4.0 ma; v cc = 3.0 v 2.6 - - v v ol low-state output voltage v i = v ih or v il i o = 20 m a; v cc = 0.8 v to 3.6 v - - 0.1 v i o = 1.1 ma; v cc = 1.1 v - - 0.3 v cc v i o = 1.7 ma; v cc = 1.4 v - - 0.31 v i o = 1.9 ma; v cc = 1.65 v - - 0.31 v i o = 2.3 ma; v cc = 2.3 v - - 0.31 v i o = 3.1 ma; v cc = 2.3 v - - 0.44 v i o = 2.7 ma; v cc = 3.0 v - - 0.31 v i o = 4.0 ma; v cc = 3.0 v - - 0.44 v i i input leakage current v i = gnd to 3.6 v; v cc = 0 v to 3.6 v - - 0.1 m a i off power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v - - 0.2 m a d i off additional power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v to 0.2 v -- 0.2 m a i cc quiescent supply current v i = gnd or v cc ; i o = 0 a; v cc = 0.8 v to 3.6 v - - 0.5 m a d i cc additional quiescent supply current v i = v cc - 0.6 v; i o = 0 a; v cc = 3.3 v --40 m a c i input capacitance v cc = 0 v to 3.6 v; v i = gnd or v cc - 1.0 - pf c o output capacitance v o = gnd; v cc = 0 v - 1.8 - pf
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 7 of 18 philips semiconductors 74aup2g04 low-power dual inverter t amb = - 40 c to +85 c v ih high-state input voltage v cc = 0.8 v 0.70 v cc -- v v cc = 0.9 v to 1.95 v 0.65 v cc -- v v cc = 2.3 v to 2.7 v 1.6 - - v v cc = 3.0 v to 3.6 v 2.0 - - v v il low-state input voltage v cc = 0.8 v - - 0.30 v cc v v cc = 0.9 v to 1.95 v - - 0.35 v cc v v cc = 2.3 v to 2.7 v - - 0.7 v v cc = 3.0 v to 3.6 v - - 0.9 v v oh high-state output voltage v i = v ih or v il i o = - 20 m a; v cc = 0.8 v to 3.6 v v cc - 0.1 - - v i o = - 1.1 ma; v cc = 1.1 v 0.7 v cc -- v i o = - 1.7 ma; v cc = 1.4 v 1.03 - - v i o = - 1.9 ma; v cc = 1.65 v 1.30 - - v i o = - 2.3 ma; v cc = 2.3 v 1.97 - - v i o = - 3.1 ma; v cc = 2.3 v 1.85 - - v i o = - 2.7 ma; v cc = 3.0 v 2.67 - - v i o = - 4.0 ma; v cc = 3.0 v 2.55 - - v v ol low-state output voltage v i = v ih or v il i o = 20 m a; v cc = 0.8 v to 3.6 v - - 0.1 v i o = 1.1 ma; v cc = 1.1 v - - 0.3 v cc v i o = 1.7 ma; v cc = 1.4 v - - 0.37 v i o = 1.9 ma; v cc = 1.65 v - - 0.35 v i o = 2.3 ma; v cc = 2.3 v - - 0.33 v i o = 3.1 ma; v cc = 2.3 v - - 0.45 v i o = 2.7 ma; v cc = 3.0 v - - 0.33 v i o = 4.0 ma; v cc = 3.0 v - - 0.45 v i i input leakage current v i = gnd to 3.6 v; v cc = 0 v to 3.6 v - - 0.5 m a i off power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v - - 0.5 m a d i off additional power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v to 0.2 v -- 0.6 m a i cc quiescent supply current v i = gnd or v cc ; i o = 0 a; v cc = 0.8 v to 3.6 v - - 0.9 m a d i cc additional quiescent supply current v i = v cc - 0.6 v; i o = 0 a; v cc = 3.3 v --50 m a table 8: static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 8 of 18 philips semiconductors 74aup2g04 low-power dual inverter t amb = - 40 c to +125 c v ih high-state input voltage v cc = 0.8 v 0.75 v cc -- v v cc = 0.9 v to 1.95 v 0.70 v cc -- v v cc = 2.3 v to 2.7 v 1.6 - - v v cc = 3.0 v to 3.6 v 2.0 - - v v il low-state input voltage v cc = 0.8 v - - 0.25 v cc v v cc = 0.9 v to 1.95 v - - 0.30 v cc v v cc = 2.3 v to 2.7 v - - 0.7 v v cc = 3.0 v to 3.6 v - - 0.9 v v oh high-state output voltage v i = v ih or v il i o = - 20 m a; v cc = 0.8 v to 3.6 v v cc - 0.11 - - v i o = - 1.1 ma; v cc = 1.1 v 0.6 v cc -- v i o = - 1.7 ma; v cc = 1.4 v 0.93 - - v i o = - 1.9 ma; v cc = 1.65 v 1.17 - - v i o = - 2.3 ma; v cc = 2.3 v 1.77 - - v i o = - 3.1 ma; v cc = 2.3 v 1.67 - - v i o = - 2.7 ma; v cc = 3.0 v 2.40 - - v i o = - 4.0 ma; v cc = 3.0 v 2.30 - - v v ol low-state output voltage v i = v ih or v il i o = 20 m a; v cc = 0.8 v to 3.6 v - - 0.11 v i o = 1.1 ma; v cc = 1.1 v - - 0.33 v cc v i o = 1.7 ma; v cc = 1.4 v - - 0.41 v i o = 1.9 ma; v cc = 1.65 v - - 0.39 v i o = 2.3 ma; v cc = 2.3 v - - 0.36 v i o = 3.1 ma; v cc = 2.3 v - - 0.50 v i o = 2.7 ma; v cc = 3.0 v - - 0.36 v i o = 4.0 ma; v cc = 3.0 v - - 0.50 v i i input leakage current v i = gnd to 3.6 v; v cc = 0 v to 3.6 v - - 0.75 m a i off power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v - - 0.75 m a d i off additional power-off leakage current v i or v o = 0 v to 3.6 v; v cc = 0 v to 0.2 v -- 0.75 m a i cc quiescent supply current v i = gnd or v cc ; i o = 0 a; v cc = 0.8 v to 3.6 v - - 1.4 m a d i cc additional quiescent supply current v i = v cc - 0.6 v; i o = 0 a; v cc = 3.3 v --75 m a table 8: static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 9 of 18 philips semiconductors 74aup2g04 low-power dual inverter 12. dynamic characteristics table 9: dynamic characteristics voltages are referenced to gnd (groun d = 0 v); for test circuit see figure 8 symbol parameter conditions min typ [1] max unit t amb = 25 c; c l = 5 pf t phl , t plh high-to-low and low-to-high propagation delay na to ny see figure 7 v cc = 0.8 v - 16.0 - ns v cc = 1.1 v to 1.3 v 2.4 5.0 10.3 ns v cc = 1.4 v to 1.6 v 1.8 3.6 6.4 ns v cc = 1.65 v to 1.95 v 1.5 2.9 5.0 ns v cc = 2.3 v to 2.7 v 1.2 2.4 3.9 ns v cc = 3.0 v to 3.6 v 1.1 2.1 3.2 ns t amb = 25 c; c l = 10 pf t phl , t plh high-to-low and low-to-high propagation delay na to ny see figure 7 v cc = 0.8 v - 19.8 - ns v cc = 1.1 v to 1.3 v 2.8 5.9 12.2 ns v cc = 1.4 v to 1.6 v 2.3 4.2 7.5 ns v cc = 1.65 v to 1.95 v 2.0 3.5 5.9 ns v cc = 2.3 v to 2.7 v 1.7 2.9 4.6 ns v cc = 3.0 v to 3.6 v 1.6 2.7 3.8 ns t amb = 25 c; c l = 15 pf t phl , t plh high-to-low and low-to-high propagation delay na to ny see figure 7 v cc = 0.8 v - 23.3 - ns v cc = 1.1 v to 1.3 v 3.2 6.7 13.0 ns v cc = 1.4 v to 1.6 v 2.6 4.7 8.6 ns v cc = 1.65 v to 1.95 v 2.3 4.0 6.7 ns v cc = 2.3 v to 2.7 v 2.1 3.3 5.1 ns v cc = 3.0 v to 3.6 v 2.0 3.1 4.2 ns t amb = 25 c; c l = 30 pf t phl , t plh high-to-low and low-to-high propagation delay na to ny see figure 7 v cc = 0.8 v - 33.6 - ns v cc = 1.1 v to 1.3 v 4.4 8.9 16.0 ns v cc = 1.4 v to 1.6 v 3.6 6.3 10.8 ns v cc = 1.65 v to 1.95 v 3.2 5.3 9.0 ns v cc = 2.3 v to 2.7 v 2.9 4.5 6.5 ns v cc = 3.0 v to 3.6 v 2.9 4.2 5.4 ns
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 10 of 18 philips semiconductors 74aup2g04 low-power dual inverter [1] all typical values are measured at nominal v cc . [2] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; s (c l v cc 2 f o ) = sum of the outputs. [3] the condition is v i = gnd to v cc . t amb = 25 c c pd power dissipation capacitance f i = 1 mhz [2] [3] v cc = 0.8 v - 2.8 - pf v cc = 1.1 v to 1.3 v - 3.0 - pf v cc = 1.4 v to 1.6 v - 3.1 - pf v cc = 1.65 v to 1.95 v - 3.2 - pf v cc = 2.3 v to 2.7 v - 3.7 - pf v cc = 3.0 v to 3.6 v - 4.3 - pf table 9: dynamic characteristics continued voltages are referenced to gnd (groun d = 0 v); for test circuit see figure 8 symbol parameter conditions min typ [1] max unit table 10: dynamic characteristics voltages are referenced to gnd (groun d = 0 v); for test circuit see figure 8 symbol parameter conditions - 40 c to +85 c - 40 c to +125 c unit min max min max c l = 5 pf t phl , t plh high-to-low and low-to-high propagation delay na to ny see figure 7 v cc = 1.1 v to 1.3 v 2.1 11.4 2.1 12.6 ns v cc = 1.4 v to 1.6 v 1.6 7.4 1.6 8.2 ns v cc = 1.65 v to 1.95 v 1.4 5.9 1.4 6.5 ns v cc = 2.3 v to 2.7 v 1.1 4.5 1.1 5.0 ns v cc = 3.0 v to 3.6 v 1.0 3.9 1.0 4.3 ns c l = 10 pf t phl , t plh high-to-low and low-to-high propagation delay na to ny see figure 7 v cc = 1.1 v to 1.3 v 2.6 13.7 2.6 15.1 ns v cc = 1.4 v to 1.6 v 2.1 8.7 2.1 9.6 ns v cc = 1.65 v to 1.95 v 1.8 7.0 1.8 7.7 ns v cc = 2.3 v to 2.7 v 1.5 5.4 1.5 6.0 ns v cc = 3.0 v to 3.6 v 1.4 4.5 1.4 5.0 ns
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 11 of 18 philips semiconductors 74aup2g04 low-power dual inverter 13. waveforms c l = 15 pf t phl , t plh high-to-low and low-to-high propagation delay na to ny see figure 7 v cc = 1.1 v to 1.3 v 3.0 15.8 3.0 17.4 ns v cc = 1.4 v to 1.6 v 2.4 10.0 2.4 11.0 ns v cc = 1.65 v to 1.95 v 2.1 8.0 2.1 8.8 ns v cc = 2.3 v to 2.7 v 1.8 6.1 1.8 6.8 ns v cc = 3.0 v to 3.6 v 1.8 5.0 1.8 5.5 ns c l = 30 pf t phl , t plh high-to-low and low-to-high propagation delay na to ny see figure 7 v cc = 1.1 v to 1.3 v 4.0 19.0 4.0 20.9 ns v cc = 1.4 v to 1.6 v 3.2 12.9 3.2 14.2 ns v cc = 1.65 v to 1.95 v 2.9 10.5 2.9 11.6 ns v cc = 2.3 v to 2.7 v 2.6 7.6 2.6 8.4 ns v cc = 3.0 v to 3.6 v 2.6 6.2 2.6 6.9 ns table 10: dynamic characteristics continued voltages are referenced to gnd (groun d = 0 v); for test circuit see figure 8 symbol parameter conditions - 40 c to +85 c - 40 c to +125 c unit min max min max measurement points are given in t ab le 11 . logic levels: v ol and v oh are typical output voltage drop that occur with the output load. fig 7. the data input (na) to output (ny) propagation delays table 11: measurement points supply voltage output input v cc v m v m v i t r = t f 0.8 v to 3.6 v 0.5 v cc 0.5 v cc v cc 3.0 ns mna344 t phl t plh v m v m v m v m na input ny output gnd v i v oh v ol
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 12 of 18 philips semiconductors 74aup2g04 low-power dual inverter [1] for measuring enable and disable times r l =5k w , for measuring propagation delays, setup and hold times and pulse width r l = 1 m w test data is given in t ab le 12 . de?nitions for test circuit: r l = load resistance c l = load capacitance including jig and probe capacitance r t = termination resistance should be equal to the output impedance z o of the pulse generator v ext = external voltage for measuring switching times. fig 8. load circuitry for switching times table 12: test data supply voltage load v ext v cc c l r l [1] t plh , t phl t pzh , t phz t pzl , t plz 0.8 v to 3.6 v 5 pf, 10 pf, 15 pf and 30 pf 5 k w or 1 m w open gnd 2 v cc 001aac521 pulse generator dut r t v i v o v ext v cc r l 5 k w c l
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 13 of 18 philips semiconductors 74aup2g04 low-power dual inverter 14. package outline fig 9. package outline sot363 (sc-88) references outline version european projection issue date iec jedec jeita sot363 sc-88 wb m b p d e 1 e pin 1 index a a 1 l p q detail x h e e v m a a b y 0 1 2 mm scale c x 13 2 4 5 6 plastic surface mounted package; 6 leads sot363 unit a 1 max b p cd e e 1 h e l p qy w v mm 0.1 0.30 0.20 2.2 1.8 0.25 0.10 1.35 1.15 0.65 e 1.3 2.2 2.0 0.2 0.1 0.2 dimensions (mm are the original dimensions) 0.45 0.15 0.25 0.15 a 1.1 0.8 97-02-28 04-11-08
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 14 of 18 philips semiconductors 74aup2g04 low-power dual inverter fig 10. package outline sot886 (xson6) terminal 1 index area references outline version european projection issue date iec jedec jeita sot886 mo-252 sot886 04-07-15 04-07-22 dimensions (mm are the original dimensions) xson6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm d e e 1 e a 1 b l l 1 e 1 0 1 2 mm scale notes 1. including plating thickness. 2. can be visible in some manufacturing processes. unit mm 0.25 0.17 1.5 1.4 0.35 0.27 a 1 max b e 1.05 0.95 d ee 1 l 0.40 0.32 l 1 0.5 0.6 a (1) max 0.5 0.04 1 6 2 5 3 4 6 (2) 4 (2) a
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 15 of 18 philips semiconductors 74aup2g04 low-power dual inverter fig 11. package outline sot891 (xson6) terminal 1 index area references outline version european projection issue date iec jedec jeita sot891 sot891 05-03-11 05-04-06 xson6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm d e e 1 e a 1 b l l 1 e 1 0 1 2 mm scale dimensions (mm are the original dimensions) unit mm 0.20 0.12 1.05 0.95 0.35 0.27 a 1 max b e 1.05 0.95 d ee 1 l 0.40 0.32 l 1 0.35 0.55 a max 0.5 0.04 1 6 2 5 3 4 a
74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 16 of 18 philips semiconductors 74aup2g04 low-power dual inverter 15. abbreviations 16. revision history table 13: abbreviations acronym description cdm charged device model cmos complementary metal oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor transistor logic table 14: revision history document id release date data sheet status change notice doc. number supersedes 74aup2g04_1 product data sheet - - -
philips semiconductors 74aup2g04 low-power dual inverter 74aup2g04_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. preliminary data sheet rev. 01.00 16 january 2006 17 of 18 17. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 19. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 20. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. 21. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 16 january 2006 document number: 74aup2g04_1 published in the netherlands philips semiconductors 74aup2g04 low-power dual inverter 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 4 8.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 10 recommended operating conditions. . . . . . . . 5 11 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 12 dynamic characteristics . . . . . . . . . . . . . . . . . . 9 13 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 17 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17 18 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 19 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 20 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 21 contact information . . . . . . . . . . . . . . . . . . . . 17

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